As feature sizes of integrated circuits (ICs) shrink, functionality traditionally found on a printed circuit board can be placed onto a single die. Currently, I/O signals, which electrically connect the die to other components, are reached through contacts surrounding the circuit on the die. The number of I/O signals is physically limited by the perimeter of the die. A widely practiced way to increase the number of available I/O signals is to use flip-chip methodology for packaging, where an array of contacts is positioned on the circuit face of the die and the die is mounted circuit face down upon a single chip or multi-chip module carrier. Flip-chip technology makes efficient use of otherwise unused area.
One method of flip-chip attachment is controlled collapsed chip connection pads (C4), pioneered by the International Business Machines Corp. (IBM) during the 1960s. An array of solder bumps corresponding to the array of contacts connects the flipped die to the multi-chip module carrier. The single chip or multi-chip structure may subsequently be packaged and mounted on a printed circuit board.
Dice destined for flip-chip attachment challenge prevailing test methodologies: full functional and at-speed. During full functional testing, the operation of the unpackaged die is evaluated while testing at-speed determines the operation of the die along with parasitic delays introduced by packaging and wiring. Current test fixtures are best suited for testing I/O signals positioned at the perimeter of the die. For flip-chip dice, these fixtures fail as all of the contact pads or solder bumps cannot be reached simultaneously without an elaborate fixture.
The delicate character of the solder bumps further complicates array testing. Solder bumps are very soft and extension of traditional probing techniques results in deformed bumps. Although the bumps can be reshaped after testing, this amounts to an unnecessary and hazardous expense. The reshaping or reflow process subjects the dice to a heating step that can injure the operation and performance of the IC.
One solution to avoid deforming the solder bumps is using cantilever shaped probe tips. The sharp probe tips provide connections that have low resistance and inductance at higher frequencies. The power/ground supplies are provided with nearby capacitive decoupling. However, the number of rows of probe tips is physically limited by the length of the probe tip. At best, as only four rows of the C4 array can be tested simultaneously, the design of the IC must be carefully planned so that a partitioned test methodology may be used. Furthermore, with a cantilever probe, horizontal deflection, a highly desirable feature that forms a good electrical contact with the solder bump by removing native oxide, cannot be controlled.
An alternate solution is a test fixture made of an array of tungsten probe tips or pogo pins and wires, such as the Cobra probe by IBM. Although the IC can be tested, the wires are unreliable and quite costly when hundreds of probe tips are needed. Furthermore, the probes deform the delicate solder bumps and the electrical models are too complex.
Other solutions include flexible membranes containing mask fabricated tips as probes. These tips lose their flexibility when multiple levels of interconnect are added. These additional connector layers are needed to test ICs operating at speeds greater than 200 MHz but render ineffective the traditional membrane probes. In addition, since the membranes cannot support discrete capacitors necessary for at-speed testing, the bypass capacitors must be remotely positioned.
Applying solder bumps to chip to carrier connections introduces a new complication during operation. Each time a die is power cycled, thermal stress is applied to the chip connection. Differential thermal expansion results when there is a material mismatch or a temperature difference between components of similar materials. Solder bumps have about a 1% freedom to be laterally distended and must be made quite tall and therefore fat. Thus the pitch of the bumps physically constrains the density of the solder bump array. Overall, this results in a shearing strain on the solder bump and may introduce subsequent reliability problems with transistors and on-chip wiring when the IC is used in operation.